電氣工程論文編號:DQ035  論文字?jǐn)?shù):11721,頁數(shù):31 附任務(wù)書，開題報告，文獻(xiàn)綜述，外文翻譯

目  錄
摘  要 I
Abstract II
目  錄 III
1  前言 1
2  8051單片機(jī)簡介 4
2.1  8051單片機(jī)的結(jié)構(gòu) 4
2.2  8051單片機(jī)與LED顯示方法 6
3  MAX+PLUS II簡介 7
3.1  Max+plusⅡ功能簡介 7
4  簡易數(shù)字頻率計的實現(xiàn)方式 10
4.1  測頻方案及其原理與誤差分析 10
4.2  等精度測頻系統(tǒng)組成 12
4.3  信號調(diào)理電路設(shè)計 13
4.4  等精度測頻電路的軟硬件設(shè)計 16
4.4.1  硬件設(shè)計 16
4.4.2  軟件設(shè)計 19
4.5  數(shù)字頻率計設(shè)計源程序 20
5  結(jié)論 23
致謝 24
參考文獻(xiàn) 25
附錄 26

摘  要
 本設(shè)計運(yùn)用VHDL語言，采用Top To Down的方法，設(shè)計了一種8位簡易的數(shù)字頻率計，并利用Isp Expert集成開發(fā)環(huán)境進(jìn)行編輯、綜合、波形仿真，并下載到CPLD器件中，經(jīng)實際電路測試，該系統(tǒng)系統(tǒng)性能可靠。主要功能有：頻率測量、周期測量和脈沖寬度測量。整個設(shè)計可以分為三個部分：方案設(shè)計、軟件設(shè)計、硬件設(shè)計。本文詳細(xì)介紹了簡易數(shù)字頻率計的軟件設(shè)計和硬件設(shè)計。
關(guān)鍵詞：EDA；VHDL；數(shù)字頻率計；波形仿真；CPLD
 
Abstract
 The use of VHDL design language, the use of Top To Down approach, designed a simple 8-bit digital frequency meter, and the use of Isp Expert integrated development environment for editing, synthesis, simulation waveforms, and downloaded to the CPLD devices, the actual circuit test, the system reliable system performance. The main features are: the frequency of measurements, the cycle measurement and pulse width measurement. The whole design can be divided into three parts: program design, software design, hardware design. This paper describes a simple digital frequency of software design and hardware design.

Key word: EDA；VHDL；digital frequency meter；Waveform Simulation；CPLD