電子機(jī)電論文編號:JD857 附開題報告,任務(wù)書,外文翻譯,原理圖和PCB,論文字?jǐn)?shù):14230,頁數(shù):46

摘要 Ⅰ
目次 Ⅲ
1 引言 1
1.1 課題設(shè)計的背景 1
1.2 課題研究的意義及發(fā)展現(xiàn)狀 2
1.3 課題研究的目標(biāo)、內(nèi)容和擬解決的關(guān)鍵問題 3
2 設(shè)計方案比較 3
2.1 數(shù)字電路設(shè)計方案 4
2.2 模擬電路設(shè)計方案 5
2.3 基于MCS-51單片機(jī)的設(shè)計方案 6
2.4 基于FPGA的設(shè)計方案 8
2.5 方案論證 10
3 基于FPGA的18路電子搶答器的工作原理 11
3.1 原理框圖 11
3.2 系統(tǒng)電路圖 12
3.3 VHDL程序設(shè)計 13
4 系統(tǒng)硬件設(shè)計 20
4.1 系統(tǒng)電路PCB圖 20
4.2 EPF10K10LC84_3芯片 21
4.3 74LS245芯片 23
4.4 74LS138芯片 24
4.5 共陰極LED數(shù)碼管 26
4.6 FPGA配置方案論證 27
5.結(jié)論 33
參考文獻(xiàn) 34
致 謝 35
附 錄 A 36

摘 要：根據(jù)畢業(yè)設(shè)計任務(wù)書的要求，基于FPGA的18路智力競賽搶答器可使整個系統(tǒng)大大簡化，運(yùn)用EDA軟件平臺中的Max + plus II軟件，設(shè)計了一款實(shí)用型智力競賽搶答器。本設(shè)計闡述了搶答器原理及其設(shè)計思路、優(yōu)化實(shí)現(xiàn)方法，并給出了設(shè)計方案、具體電路圖及VHDL語言的各模塊設(shè)計，給出了基于FPGA的VHDL源程序，通過編譯和器件編程，將編程器文件以在線配置的方式下載到PCB板的主要FPGA器件——EPF10K10LC84-3器件中，經(jīng)實(shí)際電路測試驗(yàn)證，達(dá)到了預(yù)期的設(shè)計要求。該電路不但能實(shí)現(xiàn)互鎖和自鎖，并且能用聲音和數(shù)字準(zhǔn)確提示搶答者的優(yōu)先結(jié)果，大大降低了搶答器因延時造成的搶答不準(zhǔn)確等缺點(diǎn)，具有反應(yīng)快、功能齊全、實(shí)用性強(qiáng)等特點(diǎn)。
   
關(guān)鍵詞：FPGA ；Max + plus II；EPF10K10LC84-3；搶答器；仿真

Design of the Eighteen Routes intellectual
 Contest Responder Based on FPGA

Abstract：According to the request of the design specification graduating，this design of eighteen routes intellectual contest responder based on FPGA can simplify the system.By using the EDA software platform of Max+plus II，we designed an intellectual contest device of experiment to answer the question preemptively based on FPGA.And presented each module and idiographic circuit diagram. Giving the VHDL source program that based on FPGA.By editing，compiling and device programming，files of device programming in circuit configurable are down loaded to the device of EPF10K10LC84_3 of PCB experimental plate. It achieved the expectant requirements of design after actual circuit testing and verifying.This circuit can not only realize to lock with each other and itself, but also use the voice，arithmetic figure to hint the result at the same time.Reduce the lack of wrong answering because of responder late.It facts quick,having much more function and good using.

Key words：FPGA ；Max + plus II；EPF10K10LC84-3；responder ；imitation