電子機(jī)電論文編號(hào):JD221    字?jǐn)?shù):23273,頁數(shù):67       

目  錄

第1章緒論................................................................. 1
1.1  課題背景 ..............................................................1
1.2  頻率計(jì)概述.............................................................1
1.3  頻率計(jì)發(fā)展現(xiàn)狀 ........................................................2
1.4  FPGA概述.............................................................. 3
1.5  FPGA原理及結(jié)構(gòu).........................................................5
1.5.1  查找表（Look-Up-Table)的原理與結(jié)構(gòu)...................................5
1.5.2  基于查找表（LUT)的FPGA的結(jié)構(gòu).........................................5
1.5.3  查找表結(jié)構(gòu)的FPGA邏輯實(shí)現(xiàn)原理.........................................7
1.5.4  其他類型的FPGA和PLD .................................................7
1.6  VHDL簡(jiǎn)介 ..............................................................8
第2章全同步頻率測(cè)量方法的研究 .............................................9
2.1  常用的數(shù)字頻率測(cè)量方法.................................................9
2.1.1  直接測(cè)頻法...........................................................9
2.1.2  多周期同步測(cè)頻方法 .................................................10
2.2  提高頻率測(cè)量精度的方案研究............................................12
2.2.1  采用對(duì)標(biāo)頻信號(hào)計(jì)數(shù)的修正來提高測(cè)量精度..............................12
2.2.2  相檢式多周期同步測(cè)頻法 .............................................13
2.3  全同步數(shù)字頻率計(jì)的工作原理 ...........................................15
2.3.1  全同步頻率測(cè)量的誤差分析............................................15
2.3.2  全同步數(shù)字頻率計(jì)原理框圖 ...........................................16
第3章基于FPGA器件的功能模塊電路設(shè)計(jì)...................................... 18
3.1  脈沖同步檢測(cè)電路......................................................18
3.2  計(jì)數(shù)器............................................................... 19
3.3  鎖存器............................................................... 20
3.4  乘法器............................................................... 20
3.5  除法器 ...............................................................28
3.6  控制器 ...............................................................34
3.7  譯碼電路..............................................................36
3.8  二十進(jìn)制轉(zhuǎn)換模塊......................................................36
3.9  頂層VHDL程序設(shè)計(jì)及整體仿真結(jié)果........................................39
第4章 FPGA配置方案的設(shè)計(jì)...................................................41
4.1  EPF10K30ATI144-3 FPGA芯片簡(jiǎn)介........................................ 41
4.2  EPC2配置芯片簡(jiǎn)介......................................................41
4.3  配置模式............................................................. 41
4.4  下載方式..............................................................42
4.5  硬件電路原理圖設(shè)計(jì)....................................................43
第5章 PCB系統(tǒng)板的設(shè)計(jì) .....................................................45
結(jié)論及展望................................................................ 47
結(jié)論.............................................................. ........47
展望 ......................................................................47
參考文獻(xiàn).................................................................. 50
致謝 ......................................................................51
附錄A：VHDL部分源程序 .....................................................52

摘    要
頻率是電子技術(shù)領(lǐng)域內(nèi)的一個(gè)基本參數(shù)，同時(shí)也是一個(gè)非常重要的參數(shù)穩(wěn)定的時(shí)鐘在高性能電子系統(tǒng)中有著舉足輕重的作用，直接決定系統(tǒng)性能的優(yōu)劣。隨著電子技術(shù)的發(fā)展，測(cè)頻系統(tǒng)使用時(shí)鐘的提高,測(cè)頻技術(shù)有了相當(dāng)大的發(fā)展，但不管是何種測(cè)頻方法，±1個(gè)計(jì)數(shù)誤差始終是限制測(cè)頻精度進(jìn)一步提高的一個(gè)重要因素。
本設(shè)計(jì)闡述了各種數(shù)字測(cè)頻方法的優(yōu)缺點(diǎn)。通過分析±1個(gè)計(jì)數(shù)誤差的來得出了一種新的測(cè)頻方法：檢測(cè)被測(cè)信號(hào)，時(shí)基信號(hào)的相位，當(dāng)相位同步時(shí)開計(jì)數(shù)，相位再次同步時(shí)停止計(jì)數(shù)，通過相位同步來消除計(jì)數(shù)誤差，然后再通過算得到實(shí)際頻率的大小。根據(jù)M/T法的測(cè)頻原理，已經(jīng)出現(xiàn)了等精度的測(cè)頻方法但是還存在±1的計(jì)數(shù)誤差。因此，本文根據(jù)等精度測(cè)頻原理中閘門時(shí)間只與測(cè)信號(hào)同步，而不與標(biāo)準(zhǔn)信號(hào)同步的缺點(diǎn)，通過分析已有等精度測(cè)頻方法所存±1個(gè)計(jì)數(shù)誤差的來源，采用了全同步的測(cè)頻原理在FPGA器件上實(shí)現(xiàn)了全同步字頻率計(jì)。根據(jù)全同步數(shù)字頻率計(jì)的測(cè)頻原理方框圖，采用VHDL語言，成功編寫出了設(shè)計(jì)程序，并在MAX+PLUSⅡ軟件環(huán)境中，對(duì)編寫的VHDL程序進(jìn)了仿真，得到了很好的效果。最后，又討論了全同步頻率計(jì)的硬件設(shè)計(jì)并給出了電路原理圖和PCB圖。對(duì)構(gòu)成全同步數(shù)字頻率計(jì)的每一個(gè)模塊，給出了較詳細(xì)設(shè)計(jì)方法和完整的程序設(shè)計(jì)以及仿真結(jié)果。
關(guān)鍵詞：FPGA、頻率計(jì)、VHDL語言、MAX+PLUSⅡ
Abstract
Frequency is a basic parameter of electronics field,meanwhile,it’s a very important parameter.Stable clock is very important in high performance electronics system,determining the syetem performance directly.With the development of technology of electronics,the frequency measurement system using higher clock,the frequency measurement technology has very nice development.In despite of using all other advanced frequency measurement methods,the positive and negative 1 errors was a very important factor that stop frequency measurement precision improving all through.
The design expound the advantage and disadvantage of most digital frequency measurement methods.Through analyzing the origin of the positive and negative 1 errors,got a new frequency measurement methods:checking the measured and standard signal’s phase,if the phase is synchronous,then the counters start counting,when the signal’s phase is synchronous again,the counter stopping working,by phase in-phase to eliminate counting errors,then getting the real frequency through calculating.By this way’s guide,the design of complete digital cymometer was successfully completed with using VHDL(Very High Speed Integrated Circuit Hard Design Language）hardware description language and simulated it right.According to all of Synchronous Digital Block diagram of the frequency measurement using VHDL,the successful preparation of the design process,and in MAX+PLUS II software environment,the preparation of procedures for VHDL simulation,obtained very good results.Lastly,the frequency synchronization of the whole discussion of the hardware design and gives the circuit schematics and PCB plans.All of a synchronous digital frequency of each module,is a more detailed design and integrity of the process design and simulation results.
Keyword：FPGA、Cymometer、VHDL、MAXPLUSⅡ